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Showing posts with label SNPS. Show all posts
Showing posts with label SNPS. Show all posts

Tuesday, July 24, 2012

Synopsys Mixed-Signal IC Design Solution Qualified for TowerJazz Power Management Reference Flow 2.0

News release:


Synopsys Mixed-Signal IC Design Solution Qualified for TowerJazz Power Management Reference Flow 2.0
Collaboration Delivers Comprehensive Power Management Solution
MOUNTAIN VIEW, Calif. and MIGDAL HAEMEK, Israel, July 24, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and TowerJazz (NASDAQ: TSEM, TASE: TSEM), the global specialty foundry leader, today announced that they have qualified Synopsys' unified mixed-signal IC design solution for TowerJazz's power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys' tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.
Synopsys' unified mixed-signal IC design flow includes the IC Compiler™ and Galaxy Custom Designer® physical co-design implementation solution, HSPICE® circuit simulation, CustomSim™ FastSPICE simulation, CustomSim-VCS® mixed-signal co-simulation, IC Validator physical verification, and StarRC™ parasitic extraction tools. The TowerJazz PM Reference Flow 2.0includes a reference design based on a 180-nm iPDK for the bipolar CMOS DMOS (BCD) process. The TowerJazz BCD power management process platform offers the combination of 180-nm CMOS logic density with a wide range of high-voltage power devices on a single chip to enable the design of complex power management integrated circuits (ICs).
"TowerJazz and Synopsys have an on-going collaboration to create and promote iPDKs as a standard for the custom design community," said Ori Galzur, vice president of design center and design enablement at TowerJazz. "This collaboration has now been extended to our new TowerJazz Power Management Reference Flow 2.0 and further expands our relationship to include a qualified Synopsys mixed-signal design solution that addresses the needs of power management IC design."
"As ICs become more heterogeneous with a mix of cell-based and custom implementation, designers require a unified implementation and verification solution to stay productive and competitive," said Bijan Kiani, vice president of product marketing at Synopsys. "With this foundry-qualified solution, our mutual customers will be able to more easily manage the increased complexity and aggressive development schedules of mixed-signal designs."
About SynopsysSynopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at www.synopsys.com.
About TowerJazzTower  Semiconductor  Ltd. (NASDAQ: TSEM, TASE: TSEM), the global specialty foundry leader and  its fully owned U.S. subsidiary Jazz Semiconductor, operate collectively under the brand name TowerJazz, manufacturing integrated circuits with geometries ranging from  1.0  to  0.13-micron. TowerJazz provides industry leading design enablement tools to allow complex designs to be achieved quickly and more accurately and offers a broad range of customizable process technologies including SiGe, BiCMOS, mixed-signal and RFCMOS, CMOS image sensor, power management (BCD), and non-volatile memory (NVM), as well as MEMS capabilities. To provide world-class customer service, TowerJazz maintains two manufacturing facilities in Israel and one in the U.S. with additional capacity available in China through manufacturing partnerships. For more information, please visitwww.towerjazz.com.

Latest Synopsys Virtualizer Release Speeds Virtual Prototype Creation by up to 3X

News release:


Latest Synopsys Virtualizer Release Speeds Virtual Prototype Creation by up to 3X
New Modeling Interface and Automation Increase Modeling Productivity to Enable Earlier Start of Software Development
MOUNTAIN VIEW, Calif., July 24, 2012 /PRNewswire/ --
Highlights:
  • Enhanced model authoring capability speeds the creation of SystemC-based transaction-level models used to build virtual prototypes
  • New import function reduces modeling effort and errors by automating model generation from IP specifications captured in popular formats such as IP-XACT, Excel, Word and PDF
  • New simulation profiler quickly identifies execution bottlenecks to enable faster prototype simulation performance
  • Deeper integration with popular software debuggers such as ARM Development Studio 5 (DS-5™) and Lauterbach TRACE32 System helps identify difficult bugs through multicore and context-aware debugging
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of the latest release of Synopsys' Virtualizer™ tool set for creating virtual prototypes and Virtualizer Development Kits (VDKs) that accelerate embedded software development. The new Virtualizer release improves modeling productivity through its new model authoring feature and IP specification import function, enabling engineers to develop system-level models and assemble them into virtual prototypes up to three times faster. In addition, enhanced support for popular debugger tools allows software developers to easily integrate Virtualizer-based virtual prototypes into their existing software debug flows.
"Using Virtualizer, we can abstract the full SoC design into a virtual prototype in a very short period of time to facilitate early software development and hardware/software integration," said Satoshi Aoki of the Embedded Platform Development Department at Ricoh Company, Ltd. "We believe Virtualizer is a must-have tool for SoC development."
Synopsys' Virtualizer virtual prototyping solution is an integral part of the industry's most comprehensive solution of tools, models and services for early software development, hardware/software integration, and system validation. Virtualizer addresses the increasing software complexity associated with semiconductor and electronic products by enabling the efficient creation of SystemC-based transaction-level models (TLMs), as well as the assembly of TLMs into virtual prototypes representing complete systems. The Virtualizer tool set is also used by designers to create customized VDKs, software development kits containing design-specific virtual prototypes as well as debug and analysis tools and sample software, which can be deployed to software development teams up to 12 months before silicon availability. Ready-to-use VDKs for ARM® big.LITTLE™ processing and ARM Cortex™-A15 MPCore™ processor-based designs are also available from Synopsys.
"Mitigating development risk and reducing time to market are key considerations for companies developing complex systems such as smartphones, tablets and smart-TVs," said Javier Orensanz, director of product management, system design division, ARM. "The Synopsys VDKs for ARM big.LITTLE processing and Cortex-A15 processor-based designs enable engineers to achieve optimal results by addressing these considerations. When used alongside ARM Development Studio 5 and the ARM Streamline™ performance analyzer, engineers are able to improve energy efficiency and even further reduce development risk."
This Virtualizer release incorporates a new graphical simulation profiler which makes it easier for virtual prototyping teams to find and address simulation bottlenecks. Out-of-the-box support for the latest APIs in popular software debuggers such as Lauterbach TRACE32 System and ARM Development Studio 5 (DS-5) enables software teams to use VDKs to create a powerful, integrated environment for multicore software debug. In addition, integration with MathWorks' Simulink simulation environment enables more rapid deployment of virtual hardware-in-the-loop (HIL) testing.
"The tight integration of our TRACE32 debugger with the latest Virtualizer release includes mutual support for the industry-standard Multi-Core Debug API, giving software programmers a unified and efficient environment for multicore debug and analysis," said Stephan Lauterbach, general manager at Lauterbach. "This integration enables engineers to start software development early in the design cycle on virtual prototypes without having to switch to other debug tools as they transition to real hardware."
The model authoring interface in the new Virtualizer tool set simplifies and automates model creation with new features such as automatic design rule checking and design-sensitive help, improving modeling productivity for both virtual prototyping experts as well as those less experienced. The new tool release also enables users to import existing IP specifications in popular formats such as IP-XACT, Excel, Word and PDF, further speeding model development by automatically generating SystemC Modeling Library (SCML) constructs and industry-standard Accellera Systems Initiative TLM-2.0 bus interfaces. In addition to providing improved model creation capabilities, the most recent Virtualizer release continues to support direct integration of TLM-2.0 standard-based models of common IP blocks readily available in the market, including Synopsys' DesignWare® TLM Library models, ARM Fast Models, and other SystemC TLM models available from Synopsys.  It also supports more than 900 system-level models that can be found on TLMCentral.
"Software teams are increasingly taking advantage of virtual prototypes to get an early jump on software development," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The latest release of Virtualizer makes it easier and faster than ever for design teams to create virtual prototypes and deploy them to software engineers in VDKs, enabling a significant time-to-market advantage over competitors relying on only traditional software development methods."
Availability & ResourcesThe new Virtualizer 12.06 release is available now.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Wednesday, July 18, 2012

Latest Release of Synopsys IC Compiler Enables Giga-Performance Design

News release:


Latest Release of Synopsys IC Compiler Enables Giga-Performance Design
Continued Performance Focus Fortifies Widespread Deployment at Renesas Electronics
MOUNTAIN VIEW, Calif., July 18, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the availability of the 2012.06 release of its IC Compiler™ software, featuring multiple advances to support giga-performance design. A key component of Synopsys' Galaxy™ Implementation Platform, IC Compiler has been addressing the productivity and manufacturability challenges inherent in giga-performance design through smarter optimization, faster design convergence and advanced process node support. This latest release of IC Compiler focuses on helping IC designers achieve higher clock frequencies more efficiently. New capabilities include innovative optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.
 "Renesas Electronics is a premier provider of advanced semiconductor solutions," said Tatsuji Kagatani, department manager, Back-end Design Technology Development Department at Renesas Electronics Corporation. "We rely on continuous technology innovation in IC Compiler to realize our very challenging designs with clock speed targets of well over 1 GHz and/or lower power consumption with aggressive time to market goals. In our recent study of IC Compiler's new multisource CTS technology on a design with several complex clocks, we were easily able to meet our demanding skew and latency targets."
The IC Compiler 2012.06 release contains several new technologies geared towards boosting design frequency. Clock distribution using a mesh structure has been a staple of high performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multisource clock tree synthesis (CTS) is an innovative new technology that leverages automated clock tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.
Processor designers favor the performance scalability and smaller device geometries offered at lower process nodes. In this release, new algorithms leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. With shorter time-to-market windows and the need for a more integrated feature set, designs are seeing increasing intellectual property (IP) reuse. IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. The latest IC Compiler release can improve timing and routability for such designs. The 2012.06 release also delivers several enhancements which enable designers to achieve target frequency. Transparent interface optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power network verification and improved runtime for foundry-required metal fill insertion.
 "Renesas is a dominant presence in microcontrollers and embedded SoC designs," said Michael Jackson, vice president R&D, physical implementation, Synopsys. "We have worked closely with Renesas in delivering technology enhancements to boost performance and achieve faster design closure. The results of this successful collaboration can be seen by the continued leadership of IC Compiler in the physical implementation space."
About SynopsysSynopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Monday, June 18, 2012

Synopsys Celebrates 25th Anniversary by Helping Local Students

News release:


Synopsys Celebrates 25th Anniversary by Helping Local Students
Approximately 500 volunteers will donate 3,000 hours refurbishing Lee Mathson Middle School

MOUNTAIN VIEW, Calif., June 18, 2012 /PRNewswire/ --

Highlights:
  • Refurbishment activity will take place Saturday, June 23, 2012 from 9:00 a.m.- 4:00 p.m. at Lee Mathson Middle School, San Jose, California
  • Opening ceremony speakers (9:35-10:00 a.m.)
    • Congresswoman Zoe Lofgren, California's 16th District
    • Mayor Chuck Reed, City of San Jose
    • Dr. Chi-Foon Chan, Synopsys President and co-CEO
    • Jacqueline Montejano, Lee Mathson Middle School Principal
  • The day's projects will include repainting buildings, building benches and planter boxes, weeding, planting, mural painting and more
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that it will celebrate its 25th year in business by helping transform the physical environment at Lee Mathson Middle School in the Alum Rock School District in San Jose, California. During the one-day event on June 23, 2012, approximately 500 volunteers will paint, garden, and do repair work to refurbish the school for the benefit of its students and the surrounding community. The Care Force division of City Year, a nonprofit service organization, is helping organize and manage the activity.
The volunteer event is a way for Synopsys to contribute to and thank the community that has hosted the company for over two decades. This special event complements its regular charitable giving and volunteer activities, which are an integral part of the company's culture.
"This event is particularly exciting for us because it's a real collaborative approach — a joint effort," said Brian Cabrera, general counsel and vice president, legal and corporate affairs, Synopsys. "Our employees, their family members, the Lee Mathson community and City Year will channel our collective energy and make a real and visible difference for Lee Mathson students in just one day."
Lee Mathson was chosen for the renovation project because it's an underserved school with 100 percent of its 650 students receiving free or reduced lunch. To help the at-risk student population, the school's faculty leverages all available resources. They've employed prescriptive teaching methods to meet the needs of students and have enlisted the support of City Year San Jose/Silicon Valley to help fill the education gap. For the past three years, City Year has provided young adult volunteers for "near-peer" support to the children of Lee Mathson, helping to improve student attendance, behavior and academic performance.
"Our students have great potential and show real promise; we want them to know how valued they are," said Jacqueline Montejano, principal, Lee Mathson Middle School. "The Synopsys renovation project will really send the message that they matter. I can't wait to see their expressions when they come back in the fall to a sparkling and beautiful place to learn."
Resources
  • Lee Mathson Middle School address: 2050 Kammerer Ave., San Jose, CA 95116
  • Learn more about Synopsys' 25th anniversary volunteer activity: http://bit.ly/Lku0wg
  • Follow Synopsys community relations on Twitter: http://twitter.com/synopsysshares
  • Day of contacts:
    • Yvette Huygen, director worldwide public relations, Synopsys: 650-533-9838
    • Monica Marmie, public relations senior manager, Synopsys: 408-836-3728
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing.  Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.