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IBM Helps Germany's REAL Hypermarkets Personalize Online Coupons for In-Store Shoppers

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Armonk, N.Y. - 30 Jul 2012: Major retail hypermarket chain REAL, part of Metro Group, worked with IBM (NYSE: IBM) to launch a new electronic coupon system throughout its 320 German stores. This first-of-a-kind digital coupon system, developed with IBM Research scientists, enables consumers to use their mobile phones to find and redeem e-coupons as they shop in stores. This delivers a convenient and personalized service to shoppers, even if they left their paper coupons at home.

REAL hypermarkets, which sell about 80,000 items, from food to electrical appliances to clothing, already conducts the largest coupon program in Germany through the company's "Payback" program. REAL cites customer loyalty programs such as Payback as an important part of their business strategy in the highly competitive retail market. 

REAL's coupon program enables in-store Payback members to use their mobile phones to browse online coupons as they walk through the aisles. Shoppers can choose their favorite coupons from the REAL homepage or a Payback app on their smartphones. In a maximum of 500 milliseconds, the system confirms their choice and transfers an eCoupon to the store's "3V - Value Voucher Validation" coupon system in real time. To redeem the eCoupon, customers display their Payback membership card upon check-out and the transaction is processed automatically. 

Flexible, personalized service for consumers  

For REAL, the electronic system offers a more personalized view of customers and the option to change coupon distribution in real time. Promotions can respond more flexibly to seasonal changes or fashion fads to appeal to ever-changing consumer tastes. 

"In essence, we are simplifying and improving the coupon redemption process," explains Bernd Hasenbank, Head of Point of Sale Solutions at REAL. 

"In the era of Big Data, consumers expect a superior retail experience – which puts pressure on retailers to deliver hyper-personalized services," says Falk Nieder, consultant at IBM Global Business Services. "REAL's e-couponing system demonstrates that retailers can deliver timely and customized coupons so that marketing feels more like a welcomed service." 

REAL expects that it will be receiving several hundred thousand eCoupon queries and eCoupon redemptions per day at the cash registers of it 320 stores. That is not an easy task for the underlying information technology (IT) architecture with a central server. 

The new 3V coupon system at REAL is based on existing IBM solutions at METRO Group, which are compliant with the EPC Information Services Standard (EPCIS) of EPCglobal. The system is based on IBM InfoSphere Traceability Server, a high-performance data storage device, that is able to manage and analyze large amounts of data, integrate master data systems and provide data in real-time for internal and external applications. 

About REAL

REAL - Germany is known for its comprehensive range of brand-name and private-label products that are always fresh and good value for money. In these large-format hypermarkets, customers can find products to cover all of their daily needs quickly and easily, from food to electrical appliances to clothing. real,- hypermarkets are conveniently located, large and with a clear layout.

URL: www.real-hypermarket.com

Princess Sumaya University for Technology Receives Charles Babbage Grant from Synopsys

News release:

Princess Sumaya University for Technology Receives Charles Babbage Grant from Synopsys

First in MENA Region to Establish New Full- and Semi-custom IC Design Laboratories

MOUNTAIN VIEW, Calif., May 30, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that Princess Sumaya University for Technology (PSUT) in Amman, Jordan is the first university in the Middle East and North Africa (MENA) region to receive the Charles Babbage Grant from Synopsys. Through the grant, PSUT receives licenses for Synopsys' comprehensive, industry-leading electronic design automation (EDA) software, along with curriculum support and professor training. The grant also provides new computer hardware, printers and educational equipment, enabling PSUT to create two new laboratories for full- and semi-custom integrated circuit (IC) design for 20 students.
Lack of access to commercial-grade design tools for advanced research and microelectronic design is a common issue facing universities today. Synopsys helps solve this challenge through initiatives like the Charles Babbage Grant and its Worldwide University Program, which provide select universities with design software for modern electronic design flows and leading commercial IC fabrication processes. Previous grant recipients outside of United States include the Chinese Academy of Sciences, University of Southampton, Indian Institute of Technology Kharagpur, Moscow Institute of Electronic Technology (MIET), Yerevan State University and the State Engineering University of Armenia.
"PSUT is very grateful for this grant," said Professor Issa Batarseh, PSUT president. "It will provide our engineering students with access to world-leading software and tools and allow us to enhance our curricula."
"We always welcome industry collaboration and support," Dr. Wejdan Abu Elhaija, the Dean of King Abdullah II School for Electrical Engineering, added. "We're pleased to strengthen our relationship with Synopsys."
"Supporting programs that enable semiconductor design through academia continues to be an important priority for Synopsys," said Anwar Awad, vice president of engineering of the IP/Solutions group at Synopsys. "Working with PSUT, we have been able to create an educational program that will cultivate advanced IC design skills in Jordan and prepare graduates to establish local industry." Awad formally opened the lab in a ceremony attended by PSUT students and faculty on May 28.
Synopsys and the Department of Electronics Engineering at the King Abdullah II School of Electrical Engineering at PSUT began collaborating in 2010 by establishing a microelectronics education program through a VLSI course integrated into the Electronics Engineering curriculum in IC design. In addition to EDA software and computer resources, Synopsys provides PSUT with support, advisors, faculty training and facilitates student and faculty exchanges. In 2011, Jordanian students participated in internships and joined Student Working Groups at the Synopsys Armenia Educational Department and R&D center. The students also successfully competed in the International Microelectronics Olympiad of Armenia, an annual competition that recognizes and inspires young talented engineers involved in microelectronics. PSUT and Synopsys are continuing to strengthen their cooperation in research and education. Again this year, PSUT students will intern at Synopsys Armenia and participate in theSeventh International Microelectronics Olympiad of Armenia.
About the Charles Babbage GrantThe Charles Babbage Grant provides select universities worldwide with state-of-the-art EDA tools, training, support and technology. It enables institutions of higher education to enhance their expertise in microelectronics circuits and system design. Use of the Synopsys tools on modern, powerful computers from the grant helps universities to better prepare their graduates for the future by providing hands-on experience with current industry practices, modern design techniques and actual design tools and computer hardware. This enhances the students' understanding of how learning applies to the real world of IC design. The grant is named after British mathematician and inventor Charles Babbage, who designed and built mechanical computing machines on principles that anticipated the modern electronic computers of today over 150 years ago. For more information about the Synopsys Worldwide University Program, visit us at http://www.synopsys.com/Community/UniversityProgram/Pages/default.aspx.
About Princess Sumaya University for Technology (PSUT)Founded in 1991, Princess Sumaya University for Technology is a not-for-profit, top-ranked private university offering bachelors and masters degrees in business, IT and engineering. Its location within the El-Hassan Science City and the Royal Scientific Society has granted the university a special status within the scientific matrix of Al-Jubeiha, Amman, which includes the Ministry of Higher Education & Scientific Research, the Higher Council for Science and Technology and the Royal Geographic Center. For more information, please visit the PSUT website at http://www.psut.jo/main.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

GLOBALFOUNDRIES Selects Synopsys' Yield Explorer for Faster Yield Ramp

News release:

GLOBALFOUNDRIES Selects Synopsys' Yield Explorer for Faster Yield Ramp

Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms

MOUNTAIN VIEW, Calif., May 30, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that GLOBALFOUNDRIES has selected Synopsys' Yield Explorer® solution as part of their next-phase Yield Management System (YMS) for faster yield ramp based on volume diagnostics.  Rapid identification and correction of systematic failure mechanisms is critical to bringing a new technology node to production and driving the yield ramp on new integrated circuit (IC) designs. Yield Explorer Automated Volume Diagnostics allows GLOBALFOUNDRIES to quickly identify the dominant systematic failure mechanisms on early test chips as well as customers' chips, thereby reducing the time to achieve desirable yield levels. In addition, Yield Explorer's unique ability to combine and analyze data from design, fab and test domains enables collaboration between GLOBALFOUNDRIES and its customers to rapidly identify failure mechanisms and activate process or design corrective actions with high clarity and ease.
"Understanding and preventing the yield loss caused by design-process interactions is critical to ramp-up of designs manufactured on a new node," said Robert Madge, director of design enabled manufacturing at GLOBALFOUNDRIES. "Yield Explorer is a valuable new addition to our advanced Yield Management capabilities. Yield Explorer's unique data-sharing model very effectively addresses the sensitivity of design data, allowing strong collaboration with our customers during the yield ramp phase."
Yield Explorer delivers unparalleled flexibility and depth of capabilities in correlating yield loss to various design, fab and test attributes, as well as fast, robust automation for production analysis and reporting. Expert users benefit from the flexibility to perform analysis with an exploratory approach. Production teams rely on automated analysis routines to create various reports and provide a quick first view of yield issues on new production batches with minimal impact on cycle time. Additionally, any inputs to design teams for adjusting test plans or incremental layout changes are provided with specific and actionable details about the yield- limiting attribute of test or layout. The automated volume diagnostics in Yield Explorer are simple to deploy and work smoothly across a variety of design, fab and test outputs and data formats.
"Meeting yield targets for complex designs implemented on 28-nm and below technology requires understanding the complex interactions of design, lithography and process," said Howard Ko, senior vice president and general manager, Synopsys Silicon Engineering Group. "We are excited that GLOBALFOUNDRIES has chosen Yield Explorer to help them more quickly ramp-up new nodes and new designs."
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

AMD Selects Synopsys as a Verification IP Partner

News release:

AMD Selects Synopsys as a Verification IP Partner

Expands Collaboration to Further Accelerate SoC Verification

MOUNTAIN VIEW, Calif., May 14, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery™ Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM® AMBA® AXI™ interconnect, SATA 3.0, PCI Express® Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.
"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3™ and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."
The growing use of increasingly complex interface protocols makes verification and debug of SoCs one of the most difficult and time-consuming aspects of functional verification. VIP provides functional models that engineers use to test all SoC interfaces before manufacturing, enabling them to verify whether an interface conforms to published specification. Synopsys' Discovery VIP family offers up to four times (4X) higher performance than other commercial VIP, as well as ease-of-use, ease-of-debug, configuration, coverage and test-development capabilities to improve SoC verification productivity.
"The strategic agreement announced today expands and accelerates the successful long-standing verification collaboration between AMD and Synopsys," said Manoj Gandhi, senior vice president and general manager of the Synopsys Verification Group. "With the increasingly critical nature of VIP in SoC verification, we continue to collaborate with AMD to deliver leading VIP technology that helps manage the total cost of verification."
About Synopsys®
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Samsung Electronics Tapes out Gigahertz+ ARM Cortex-A15 Processor with Synopsys IC Compiler

Press Release:

Samsung Electronics Tapes out Gigahertz+ ARM Cortex-A15 Processor with Synopsys IC Compiler

Hardened core used in industry's first ARM® Cortex™-A15 processor-based SoC for mobile computing devices

MOUNTAIN VIEW, Calif., April 30, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the successful collaboration between Synopsys and Samsung Electronics on the implementation of an ARM Cortex-A15 MPCore™ processor. The processor core was implemented by Samsung Austin Research Center (SARC) using Synopsys IC Compiler place-and-route technology, a cornerstone of the Synopsys Galaxy™ Implementation Platform. Running at operating speeds in excess of a gigahertz on Samsung's 32nm low power process, the hardened core has already been deployed in the industry's first Cortex-A15 processor-based SoC for mobile computing devices. The high speed was enabled through a unique combination of innovative optimization techniques and differentiated high-performance technologies which have made IC Compiler the tool of choice for high-performance designs across multiple process nodes.
"Our mission is to deliver the highest frequency while minimizing power for high-end processor and graphics cores targeted to the mobile computing and digital home markets," said Keith Hawkins, vice president, SARC. "Globally, this was the first production tapeout of a Cortex-A15 processor and we relied exclusively on IC Compiler and the Galaxy tool suite to predictably achieve our performance and power targets."
Samsung fabricated the three–million-instance, dual-core Cortex-A15 processor on a 32LP high-K metal gate (HKMG) process. Synopsys collaborated closely with SARC on an implementation methodology based on key high performance technologies and optimization techniques in the Galaxy Implementation Platform to meet Samsung's stringent mass production criteria for an on-time tapeout. The processor core relied on Physical Datapath in Design Compiler® Topographical and IC Compiler for the structured placement of registers to meet power and area objectives. Layout-based debug with Design Compiler Topographical allowed quick analysis of library, netlist and placement issues to close timing. Clock mesh in IC Compiler and PrimeTime® provided the low skew and increased on-chip-variation (OCV) tolerance necessary for the high-performance core.
"Samsung is a leading provider of silicon in the mobile computing market, as can be seen by its smart phone and tablet market penetration," said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "Being at the forefront of next generation mobile products, Samsung has driven many of the technology innovations that have reinforced the position of IC Compiler as the leading choice for high-performance design. The benefits of our ongoing partnership can be seen in the impressive level of performance delivered by this gigahertz-plus processor core."
About Synopsys®
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.